Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 784

19.1.41 MA—Message Signaled Interrupt Message Address
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 84h
Default Value:
Bit
Address (ADDR) — R/W. Lower 32 bits of the system specified message address,
31:2
always DW aligned.
1:0 Reserved
19.1.42 MD—Message Signaled Interrupt Message Data Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 88h
Default Value:
Bit
Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is
15:0 enabled. Its content is driven onto the lower word (PCI AD[15:0]) during the data
phase of the MSI memory write transaction.
19.1.43 SVCAP—Subsystem Vendor Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 90h
Default Value:
Bit
15:8 Next Capability (NEXT) — RO. Indicates the location of the next pointer in the list.
Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge
7:0
subsystem vendor capability.
19.1.44 SVID—Subsystem Vendor Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 94h
Default Value:
Bit
Subsystem Identifier (SID) — R/WO. Indicates the subsystem as identified by the
31:16 vendor. This field is write once and is locked down until a bridge reset occurs (not the
PCI bus reset).
Subsystem Vendor Identifier (SVID) — R/WO. Indicates the manufacturer of the
15:0 subsystem. This field is write once and is locked down until a bridge reset occurs (not
the PCI bus reset).
784
87h
–
00000000h
89h
–
0000h
91h
–
A00Dh
97h
–
00000000h
PCI Express* Configuration Registers
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
Attribute: R/WO
Size: 32 bits
Description
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