When Sub Class Code Register (D31:F2:Offset 0Ah) = 01H - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

SATA Controller Registers (D31:F2)
14.1.5 RID—Revision Identification Register (SATA—D31:F2)
Offset Address: 08h
Default Value:
Bit
Revision ID — RO. See the Intel
7:0
of the RID Register.
14.1.6 PI—Programming Interface Register (SATA–D31:F2)
14.1.6.1

When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h

Address Offset: 09h
Default Value:
Bit
7
6:4
3
2
1
0
Datasheet
See bit description
8Ah
This read-only bit is a 1 to indicate that the PCH supports bus master operation
Reserved. Will always return 0.
Secondary Mode Native Capable (SNC) — RO. Hardwired to '1' to indicate secondary
controller supports both legacy and native modes.
Secondary Mode Native Enable (SNE) — R/W.
Determines the mode that the secondary channel is operating in.
0 = Secondary controller operating in legacy (compatibility) mode
1 = Secondary controller operating in native PCI mode.
If this bit is set by software, then the PNE bit (bit 0 of this register) must also be set by
software. While in theory these bits can be programmed separately, such a
configuration is not supported by hardware.
Primary Mode Native Capable (PNC) — RO. Hardwired to '1' to indicate primary
controller supports both legacy and native modes.
Primary Mode Native Enable (PNE) — R/W.
Determines the mode that the primary channel is operating in.
0 = Primary controller operating in legacy (compatibility) mode.
1 = Primary controller operating in native PCI mode.
If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by
software simultaneously.
Attribute:
Size:
Description
®
6 Series Chipset Specification Update for the value
Attribute:
Size:
Description
RO
8 bits
R/W, RO
8 bits
555