Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 332

Table 8-36. Power Sequencing and Reset Signal Timings (Sheet 2 of 2)
Sym
t225
t226
t227
t229
t230
t231
t232
t233
t234
t235
t236
t237
t238
t239
t240
t241
t242
t244
t246
t247
t251
t252
t253
t254
NOTES:
332
Parameter
VccRTC active to VccDSW3_3 active
RTCRST# deassertion to RSMRST#
deassertion
VccSus active to VccASW active
VccASW active to Vcc active
APWROK high to PWROK high
PWROK low to Vcc falling
APWROK falling to VccASW falling
SLP_S3# assertion to VccCore rail
falling
DPWROK falling to VccDSW rail falling
RSMRST# assertion to VccSUS rail
falling
RTCRST# deassertion to VccRTC rail
falling
SLP_LAN# (or LANPHYPC) rising to
Intel LAN Phy power high and stable
DPWROK falling to any of VccDSW,
VccSUS, VccASW, VccASW3_3, or Vcc
falling
V5REF_Sus active to VccSus3_3 active
V5REF active to Vcc3_3 active
VccSus supplies active to Vcc supplies
active
HDA_RST# active low pulse width
VccSus active to SLP_S5#, SLP_S4#,
SLP_S3#, SUS_STAT#, PLTRST# and
PCIRST# valid
S4 Wake Event to SLP_S4# inactive
(S4 Wake)
S3 Wake Event to SLP_S3# inactive
(S3 Wake)
RSMRST# deassertion to APWROK
assertion
THRMTRIP# active to SLP_S3#,
SLP_S4#, SLP_S5# active
RSMRST# rising edge transition from
20% to 80%
RSMRST# falling edge transition
Electrical Characteristics
Min Max Units
0 — ms
20 — ns
0 — ms
0 — ms
0 — ms
40 — ns
40 — ns
5 — µs
40 ns
40 — ns
0 — ms
— 20 ms
40 — ns
0 — ms
See
note — ms
15
0 — ms
1 — s
— 50 ns
See Note Below
See Note Below
0 — ms
— 175 ns
— 50 s
— 50 µs
Notes Fig
1, 12 8-2
8-2
1
13, 14,
15
15
13, 14
8-7
1, 14,
8-7
15
8-7
1, 13,
14, 15
16
16
1, 13
20
5
6
18, 19
Datasheet