Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 556

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h
Address Offset: 09h
Default Value:
Bit
7:0
14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h
Address Offset: 09h
Default Value:
Bit
7:0
14.1.7 SCC—Sub Class Code Register (SATA–D31:F2)
Address Offset: 0Ah
Default Value:
Bit
7:0
14.1.8 BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2)
Address Offset: 0Bh
Default Value:
Bit
7:0
556
00h
Interface (IF) — RO.
When configured as RAID, this register becomes read only 0.
01h
Interface (IF) — RO.
Indicates that the SATA Controller is an AHCI HBA that has a major revision of 1.
See bit description
Sub Class Code (SCC)
This field specifies the sub-class code of the controller, per the table below:
MAP.SMS (D31:F2:Offset
90h:bit 7:6) Value
00b
01b
10b
NOTE: Not all SCC values may be available for a given SKU. See
on storage controller capabilities.
01h
Base Class Code (BCC) — RO.
01h = Mass storage device
SATA Controller Registers (D31:F2)
Attribute:
Size:
Description
Attribute:
Size:
Description
Attribute:
Size:
Description
SCC Register Value
01h (IDE Controller)
06h (AHCI Controller)
04h (RAID Controller)
Attribute:
Size:
Description
RO
8 bits
RO
8 bits
RO
8 bits
Section 1.3 for details
RO
8 bits
Datasheet