Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 407

Chipset Configuration Registers
Bit
21
20
19
18
17
16
15:6
5
4:1
0
10.1.76 FDSW—Function Disable SUS Well
Offset Address: 3420h
Default Value:
Bit
7
6:0
Datasheet
High Definition Audio Static Clock Gate Enable — R/W.
0 = High Definition Audio Static Clock Gating is Disabled
1 = High Definition Audio Static Clock Gating is Enabled
USB EHCI Static Clock Gate Enable — R/W.
0 = USB EHCI Static Clock Gating is Disabled
1 = USB EHCI Static Clock Gating is Enabled
USB EHCI Dynamic Clock Gate Enable — R/W.
0 = USB EHCI Dynamic Clock Gating is Disabled
1 = USB EHCI Dynamic Clock Gating is Enabled
SATA Port 5 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 5 Dynamic Clock Gating is Disabled
1 = SATA Port 5 Dynamic Clock Gating is Enabled
SATA Port 4 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 4 Dynamic Clock Gating is Disabled
1 = SATA Port 4 Dynamic Clock Gating is Enabled
PCI Dynamic Gate Enable — R/W.
0 = PCI Dynamic Gating is Disabled
1 = PCI Dynamic Gating is Enabled
Reserved
SMBus Clock Gating Enable (SMBCGEN) — R/W.
0 = SMBus Clock Gating is Disabled.
1 = SMBus Clock Gating is Enabled.
Reserved
PCI Express Root Port Static Clock Gate Enable — R/W.
0 = PCI Express root port Static Clock Gating is Disabled
1 = PCI Express root port Static Clock Gating is Enabled
00h
Function Disable SUS Well Lockdown (FDSWL)— R/W03
0 = FDSW registers are not locked down
1 = FDSW registers are locked down
NOTE: This bit must be set when Intel
Reserved
Description
Attribute: R/W
Size: 8-bit
Description
®
Active Management Technology is enabled.
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