Power Management Pci Register Address Map (Pm-D31:F0) - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

13.8 Power Management Registers
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicated, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
13.8.1 Power Management PCI Configuration Registers
(PM—D31:F0)
Table 13-9
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
Table 13-9. Power Management PCI Register Address Map (PM—D31:F0)
Offset
A0h–A1h
A2h
A4h–A5h
A6h
A9h
AA
ABh
ACh–AFh
B8h–BBh
506
shows a small part of the configuration space for PCI Device 31: Function 0.
Mnemonic
General Power Management
GEN_PMCON_1
Configuration 1
General Power Management
GEN_PMCON_2
Configuration 2
General Power Management
GEN_PMCON_3
Configuration 3
GEN_PMCON_LO General Power Management
CK Configuration Lock
CIR4 Chipset Initialization Register 4
BM_BREAK_EN_2 BM_BREAK_EN Register #2
BM_BREAK_EN BM_BREAK_EN Register
PMIR Power Management Initialization
GPI_ROUT GPI Route Control
LPC Interface Bridge Registers (D31:F0)
Register Name Default Type
R/W, R/WO,
0000h
RO
R/W, R/WC,
00h
RO
4206h R/W, R/WC
00h RO, R/WLO
03h R/W
00h R/W, RO
00h R/W
00000000h R/W
00000000h R/W
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