Port [5:0] Dma Register Address Map - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

SATA Controller Registers (D31:F2)
14.4.2 Port Registers (D31:F2)
Ports not available will result in the corresponding Port DMA register space being
reserved. The controller shall ignore writes to the reserved space on write cycles and
shall return 0 on read cycle accesses to the reserved location.
Table 14-5. Port [5:0] DMA Register Address Map (Sheet 1 of 3)
ABAR +
Offset
100h–103h
104h–107h
108h–10Bh
10Ch–10Fh
110h–113h
114h–117h
118h–11Bh
11Ch–11Fh
120h–123h
124h–127h
128h–12Bh
12Ch–12Fh
130h–133h
134h–137h
138h–13Bh
13Ch–17Fh
180h–183h
184h–187h
188h–18Bh
18Ch–18Fh
190h–193h
194h–197h
198h–19Bh
19Ch–19Fh
1A0h–1A3h
1A4h–1A7h
1A8h–1ABh
1ACh–1AFh
1B0h–1B3h
1B4h–1B7h
1B8h–1BBh
1BCh–1FFh
Datasheet
Mnemonic
P0CLB Port 0 Command List Base Address
P0CLBU Port 0 Command List Base Address Upper 32-Bits
P0FB Port 0 FIS Base Address
P0FBU Port 0 FIS Base Address Upper 32-Bits
P0IS Port 0 Interrupt Status
P0IE Port 0 Interrupt Enable
P0CMD Port 0 Command
— Reserved
P0TFD Port 0 Task File Data
P0SIG Port 0 Signature
P0SSTS Port 0 Serial ATA Status
P0SCTL Port 0 Serial ATA Control
P0SERR Port 0 Serial ATA Error
P0SACT Port 0 Serial ATA Active
P0CI Port 0 Command Issue
— Reserved
P1CLB Port 1 Command List Base Address
P1CLBU Port 1 Command List Base Address Upper 32-Bits
P1FB Port 1 FIS Base Address
P1FBU Port 1 FIS Base Address Upper 32-Bits
P1IS Port 1 Interrupt Status
P1IE Port 1 Interrupt Enable
P1CMD Port 1 Command
— Reserved
P1TFD Port 1 Task File Data
P1SIG Port 1 Signature
P1SSTS Port 1 Serial ATA Status
P1SCTL Port 1 Serial ATA Control
P1SERR Port 1 Serial ATA Error
P1SACT Port 1 Serial ATA Active
P1CI Port 1 Command Issue
— Reserved
Register
599