Power Planes For Input Signals; Power Plane For Input Signals For Desktop Configurations - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

PCH Pin States
20. Pin-state indicates SUSPWRDNACK in Non-Deep S4/S5, Deep S4/S5 after RTC power
failure.
21. Pin-state indicates SUSWARN# in Deep S4/S5 supported platforms.
22. When Controller Reset Bit of Global Control Register (D27:F0 Offset HDBAR 08h Bit 0) gets
set, this pin will start toggling.
23. Not all signals or pin functionalities may be available on a given SKU. See
Chapter 2
3.3

Power Planes for Input Signals

Table 3-4
well as what device drives the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
PCH suspend well signal states are indeterminate and undefined and may glitch prior to
RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4#, and SLP_S5#.
These signals are determinate and defined prior to RSMRST# deassertion.
PCH core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. This does not apply to THRMTRIP#. This signal is determinate and
defined prior to PWROK assertion.
DSW indicates PCH Deep S4/S5 Well. This state provides a few wake events and critical
context to allow system to draw minimal power in S4 or S5 states.
ASW indicates PCH Active Sleep Well. This power well contains functionality associated
with active usage models while the host system is in Sx.
Table 3-4. Power Plane for Input Signals for Desktop Configurations (Sheet 1 of 3)
Signal Name
DMI[3:0]RXP,
DMI[3:0]RXN
PER[8:1]p, PERn[8:1]n
REQ0#,
1
REQ1# / GPIO50
1
REQ2# / GPIO52
1
REQ3# / GPIO54
PME#
SERR#
LDRQ0#
1
LDRQ1# / GPIO23
Datasheet
for details.
and Table 3-5 shows the power plane associated with each input signal, as
Power Well Driver During Reset
Core
PCI Express*
Core PCI Express Device
Core External Pull-up
Suspend Internal Pull-up
Core PCI Bus Peripherals
LPC Interface
Core
Core
S0/S1
DMI
Processor Driven
Driven
PCI Bus
Driven
Driven
Driven
LPC Devices Driven
LPC Devices Driven
Section 1.3 and
S3 S4/S5
Off Off
Off Off
Off Off
Driven Driven
Off Off
Off Off
Off Off
107