Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 846

22.1.1 VID—Vendor Identification
Offset Address: 00h
Default Value:
Lockable:
Bit
15:0
22.1.2 DID—Device Identification
Offset Address: 02h
Default Value:
Bit
15:0
22.1.3 CMD—Command
Address Offset: 04h
Default Value:
Bit
15:11
10
9
8
7
6
5
4
3
2
1
0
846
01h
–
8086h
No
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
03h
–
1C24h
Device ID (DID) — RO. Indicates the device number assigned by the SIG.
05h
–
0000h
Reserved
Interrupt Disable (ID) — R/W. Enables the device to assert an INTx#.
0 = When cleared, the INTx# signal may be asserted.
1 = When set, the Thermal logic's INTx# signal will be deasserted.
FBE (Fast Back to Back Enable) — RO. Not implemented. Hardwired to 0.
SEN (SERR Enable) — RO. Not implemented. Hardwired to 0.
WCC (Wait Cycle Control) — RO. Not implemented. Hardwired to 0.
PER (Parity Error Response) — RO. Not implemented. Hardwired to 0.
VPS (VGA Palette Snoop) — RO. Not implemented. Hardwired to 0.
MWI (Memory Write and Invalidate Enable) — RO. Not implemented. Hardwired to 0.
SCE (Special Cycle Enable) — RO. Not implemented. Hardwired to 0.
BME (Bus Master Enable) — R/W.
0 = Function disabled as bus master.
1 = Function enabled as bus master.
Memory Space Enable (MSE) — R/W.
0 = Disable
1 = Enable. Enables memory space accesses to the Thermal registers.
IOS (I/O Space) — RO. The Thermal logic does not implement IO Space; therefore,
this bit is hardwired to 0.
Thermal Sensor Registers (D31:F6)
Attribute: RO
Size: 16 bit
Power Well: Core
Description
Attribute: RO
Size: 16 bits
Description
Attribute: RO, R/W
Size: 16 bits
Description
Datasheet