Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 770

19.1.23 CLIST—Capabilities List Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 40–41h
Default Value:
Bit
15:8 Next Capability (NEXT) — RO. Value of 80h indicates the location of the next pointer.
7:0 Capability ID (CID) — RO. Indicates this is a PCI Express* capability.
19.1.24 XCAP—PCI Express* Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 42h–43h
Default Value:
Bit
15:14 Reserved
Interrupt Message Number (IMN) — RO. The PCH does not have multiple MSI
13:9
interrupt numbers.
Slot Implemented (SI) — R/WO. Indicates whether the root port is connected to a
8 slot. Slot support is platform specific. BIOS programs this field, and it is maintained
until a platform reset.
7:4 Device / Port Type (DT) — RO. Indicates this is a PCI Express* root port.
3:0 Capability Version (CV) — RO. Indicates PCI Express 2.0.
770
8010h
0042h
PCI Express* Configuration Registers
Attribute: RO
Size: 16 bits
Description
Attribute: R/WO, RO
Size: 16 bits
Description
Datasheet