Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 774

19.1.28 LCAP—Link Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 4Ch
Default Value:
Bit
Port Number (PN) — RO. Indicates the port number for the root port. This value is
different for each implemented port:
31:24
23:21 Reserved
Link Active Reporting Capable (LARC) — RO. Hardwired to 1 to indicate that this
20 port supports the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine.
19:18 Reserved
L1 Exit Latency (EL1) — R/WO.
000b = Less than 1us
001b = 1 us to less than 2 us
010b = 2 us to less than 4 us
17:15 011b = 4 us to less than 8 us
100b = 8 us to less than 16 us
101b = 16 us to less than 32 us
110b = 32 us to 64 us
111b = more than 64 us
L0s Exit Latency (EL0) — RO. Indicates as exit latency based upon common-clock
configuration.
14:12
NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5/F6/F7:50h:bit 6
774
4Fh
–
See bit description
Function Port #
D28:F0 1
D28:F1 2
D28:F2 3
D28:F3 4
D28:F4 5
D28:F5 6
D28:F6 7
D28:F7 8
LCLT.CCC
0 MPC.UCEL (D28:F0/F1/F2/F3:D8h:bits20:18)
1 MPC.CCEL (D28:F0/F1/F2/F3:D8h:bits17:15)
PCI Express* Configuration Registers
Attribute:
Size:
Description
Value of PN Field
01h
02h
03h
04h
05h
06h
07h
08h
Value of EL0 (these bits)
R/WO, RO
32 bits
Datasheet