Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 569

SATA Controller Registers (D31:F2)
Bits
9
8
7:6
5
4
3
2
1
Datasheet
Port 1 Present (P1P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled using P1E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 1 has been detected.
Port 0 Present (P0P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled using P0E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 0 has been detected.
Reserved
Port 5 Enabled (P5E) — R/W / RO.
0 = Disabled. The port is in the 'off' state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTES:
1. This bit takes precedence over P5CMD.SUD (offset ABAR+398h:bit 1)
2. If MAP.SC is 0, SCC is 01h, or MAP.SPD[5] is 1h, then this bit will be read only
0.
Port 4 Enabled (P4E) — R/W / RO.
0 = Disabled. The port is in the 'off' state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE:
1. This bit takes precedence over P4CMD.SUD (offset ABAR+318h:bit 1)
2. If MAP.SC is 0, SCC is 01h, or MAP.SPD[4] is 1h, then this bit will be read only
0.
Port 3 Enabled (P3E) — R/W / RO.
0 = Disabled. The port is in the 'off' state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTES:
1. This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1). When
MAP.SPD[3] is 1 this is reserved and is read-only 0.
2. Bit may be Reserved and RO depending on if port is available in the given SKU.
See Section 1.3 for details if port is available.
Port 2 Enabled (P2E) — R/W / RO.
0 = Disabled. The port is in the 'off' state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTES:
1. This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1). When
MAP.SPD[2] is 1 this is reserved and is read-only 0.
2. Bit may be Reserved and RO depending on if port is available in the given SKU.
See Section 1.3 for details if port is available.
Port 1 Enabled (P1E) — R/W / RO.
0 = Disabled. The port is in the 'off' state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1). When
MAP.SPD[1] is 1 this is reserved and is read-only 0.
Description
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