Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 886

23.2.20 MC—Message Signaled Interrupt Message Control Register
(MEI—D22:F1)
Address Offset: 8Eh–8Fh
Default Value:
Bit
15:8 Reserved.
64 Bit Address Capable (C64) — RO. Specifies that function is capable of generating
7
64-bit messages.
6:1 Reserved
MSI Enable (MSIE) — R/W. If set, MSI is enabled and traditional interrupt pins are
0
not used to generate interrupts.
23.2.21 MA—Message Signaled Interrupt Message Address
Register
(MEI—D22:F1)
Address Offset: 90h–93h
Default Value:
Bit
Address (ADDR) — R/W. Lower 32 bits of the system specified message address,
31:2
always DW aligned.
1:0 Reserved.
23.2.22 MUA—Message Signaled Interrupt Upper Address Register
(MEI—D22:F1)
Address Offset: 94h–97h
Default Value:
Bit
Upper Address (UADDR) — R/W. Upper 32 bits of the system specified message
31:0
address, always DW aligned.
23.2.23 MD—Message Signaled Interrupt Message Data Register
(MEI—D22:F1)
Address Offset: 98h–99h
Default Value:
Bit
Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is
15:0 enabled. Its content is driven during the data phase of the MSI memory write
transaction.
886
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
0080h
00000000h
00000000h
0000h
Attribute: R/W, RO
Size: 16 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 16 bits
Description
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