Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 492

13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
Offset Address: 4D1h
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Bit
IRQ15 ECL — R/W.
7
0 = Edge
1 = Level
IRQ14 ECL — R/W.
6
0 = Edge
1 = Level
5 Reserved. Must be 0.
IRQ12 ECL — R/W.
4
0 = Edge
1 = Level
IRQ11 ECL — R/W.
3
0 = Edge
1 = Level
IRQ10 ECL — R/W.
2
0 = Edge
1 = Level
IRQ9 ECL — R/W.
1
0 = Edge
1 = Level
0 Reserved. Must be 0.
492
00h
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 8 bits
Description
Datasheet