Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 608

Bit
25
24
23
22
21
20
19
18
17:16
15
14
13
608
Drive LED on ATAPI Enable (DLAE) — R/W. When set to 1, the PCH will drive the
LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA
commands. When cleared, the PCH will only drive the LED pin active for ATA
commands. See Section 5.16.10
Device is ATAPI (ATAPI) — R/W. When set to 1, the connected device is an ATAPI
device. This bit is used by the PCH to control whether or not to generate the desktop
LED when commands are active. See
Automatic Partial Slumber Transitions Enabled (APSTE)— R/W.
0 = This port will not perform Automatic Partial to Slumber Transitions.
1 = The HBA may perform Automatic Partial to Slumber Transitions.
NOTE: Software should only set this bit to '1' if CAP2.APST is set to '1'.
SATA Initalization Field — R/WO
BIOS must write a 0 to this field.
This field is not reset by FLR.
External SATA Port (ESP) — R/WO.
0 = This port supports internal SATA devices only.
1 = This port will be used with an external SATA device and hot plug is supported.
When set, CAP.SXS must also be set.
This bit is not reset by Function Level Reset.
Reserved
Mechanical Switch Attached to Port (MPSP) — R/WO. If set to 1, the PCH
supports a mechanical presence switch attached to this port.
The PCH takes no action on the state of this bit – it is for system software only. For
example, if this bit is cleared, and an mechanical presence switch toggles, the PCH
still treats it as a proper mechanical presence switch event.
NOTE: This bit is not reset on a Controller reset or by a Function Level Reset.
Hot Plug Capable Port (HPCP) — R/WO.
0 = Port is not capable of Hot-Plug.
1 = Port is Hot-Plug capable.
This indicates whether the platform exposes this port to a device which can be Hot-
Plugged. SATA by definition is hot-pluggable, but not all platforms are constructed to
allow the device to be removed (it may be screwed into the chassis, for example).
This bit can be used by system software to indicate a feature such as "eject device" to
the end-user. The PCH takes no action on the state of this bit — it is for system
software only. For example, if this bit is cleared, and a Hot-Plug event occurs, the PCH
still treats it as a proper Hot-Plug event.
NOTE: This bit is not reset on a Controller reset or by a Function Level Reset.
Reserved
Controller Running (CR) — RO. When this bit is set, the DMA engines for a port are
running.
FIS Receive Running (FR) — RO. When set, the FIS Receive DMA engine for the
port is running.
Mechanical Presence Switch State (MPSS) — RO. The MPSS bit reports the state
of a mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the
mechanical presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set
to 1 and the mechanical presence switch is open then this bit is set to 1. If CAP.SMPS
is set to '0' then this bit is cleared to 0. Software should only use this bit if both
CAP.SMPS and PxCMD.MPSP are set to 1.
SATA Controller Registers (D31:F2)
Description
for details on the activity LED.
Section 5.16.10 for details on the activity LED.
Datasheet