Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 594

14.4.1.4 PI—Ports Implemented Register (D31:F2)
Address Offset: ABAR + 0Ch–0Fh
Default Value:
Function Level Reset:No
This register indicates which ports are exposed to the PCH. It is loaded by platform
BIOS. It indicates which ports that the device supports are available for software to
use. For ports that are not available, software must not read or write to registers within
that port. After BIOS issues initial write to this register, BIOS is requested to issue two
reads to this register. If BIOS accesses any of the port specific AHCI address range
before setting PI bit, BIOS is required to read the PI register before the initial write to
the PI register.
Bit
31:6
5
4
3
2
1
0
594
00000000h
Reserved. Returns 0.
Ports Implemented Port 5 (PI5) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
This bit is read-only 0 if MAP.SC = 0 or SCC = 01h.
Ports Implemented Port 4 (PI4) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
This bit is read-only 0 if MAP.SC = 0 or SCC = 01h.
Ports Implemented Port 3 (PI3) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
NOTE: Bit may be Reserved and RO '0' depending on if port is available in the given
SKU. See Section 1.3
Ports Implemented Port 2 (PI2)— R/WO.
0 = The port is not implemented.
1 = The port is implemented.
NOTE: Bit may be Reserved and RO '0' depending on if port is available in the given
SKU. See Section 1.3
Ports Implemented Port 1 (PI1) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
Ports Implemented Port 0 (PI0) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
SATA Controller Registers (D31:F2)
Attribute:
Size:
Description
for details if port is available.
for details if port is available.
R/WO, RO
32 bits
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