Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 646

16.1.9 PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Dh
Default Value:
Bit
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI
7:0 controller is internally implemented with arbitration on an interface (and not PCI), it
does not need a master latency timer.
16.1.10 HEADTYP—Header Type Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Eh
Default Value:
Bit
7
6:0
16.1.11 MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 10h
Default Value:
Bit
Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10],
31:10
respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
9:4 Reserved
Prefetchable — RO. Hardwired to 0 indicating that this range should not be
3
prefetched.
Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere
2:1
within 32-bit address space.
Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base
0
address field in this register maps to memory space.
646
00h
80h
Multi-Function Device — RO. When set to '1' indicates this is a multifunction device:
0 = Single-function device
1 = Multi-function device.
Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration
layout.
13h
–
00000000h
EHCI Controller Registers (D29:F0, D26:F0)
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Datasheet