Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 427

PCI-to-PCI Bridge Registers (D30:F0)
11.1.20 SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0)
Offset Address: 40h–41h
Default Value:
This register allows software to hide the PCI devices, either plugged into slots or on the
motherboard.
Bit
15:4
3
2
1
0
11.1.21 DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0)
Offset Address: 44h
Default Value:
Bit
Discard Delayed Transactions (DDT) — R/W.
0 = Logged delayed transactions are kept.
1 = The PCH PCI bridge will discard any delayed transactions it has logged. This
31
NOTES:If a transaction is running on PCI at the time this bit is set, that transaction will
Block Delayed Transactions (BDT) — R/W.
0 = Delayed transactions accepted
30
1 = The PCH PCI bridge will not accept incoming transactions which will result in
29:8 Reserved
Datasheet
0000h
Reserved
Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3
(AD[19])
Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2
(AD[18])
Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1
(AD[17])
Hide Device 0 (HD0) — R/W, RO.
0 = The PCI configuration cycles for this slot are not affected.
1 = The PCH hides device 0 on the PCI bus. This is done by masking the IDSEL
(keeping it low) for configuration cycles to that device. Since the device will not see
its IDSEL go active, it will not respond to PCI configuration cycles and the
processor will think the device is not present. AD[16] is used as IDSEL for device 0.
47h
–
00000000h
includes transactions in the pending queue, and any transactions in the active
queue, whether in the hard or soft DT state. The prefetchers will be disabled and
return to an idle state.
continue until either the PCI master disconnects (by deasserting FRAME#) or
the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI
bridge when the delayed transaction queues are empty and have returned to an
idle state. Software sets this bit and polls for its completion.
delayed transactions. It will blindly retry these cycles by asserting STOP#. All
postable cycles (memory writes) will still be accepted.
Attribute: R/W, RO
Size: 16 bits
Description
Attribute: R/W
Size: 32 bits
Description
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