Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 700

17.1.1.37 PVCCAP1—Port VC Capability Register 1
®
(Intel
Address Offset: 104h–107h
Default Value:
Bit
31:12 Reserved.
11:10 Port Arbitration Table Entry Size — RO. Hardwired to 0 since this is an endpoint device.
9:8 Reference Clock — RO. Hardwired to 0 since this is an endpoint device.
7 Reserved.
Low Priority Extended VC Count — RO. Hardwired to 0. Indicates that only VC0 belongs
6:4
to the low priority VC group.
3 Reserved.
Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in
2:0
addition to VC0) is supported by the Intel
17.1.1.38 PVCCAP2 — Port VC Capability Register 2
®
(Intel
Address Offset: 108h–10Bh
Default Value:
Bit
VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration table
31:24
is not present.
23:8 Reserved.
VC Arbitration Capability — RO. Hardwired to 0. These bits are not applicable since the
7:0 Intel
Count bits in the PVCCAP1 register.
17.1.1.39 PVCCTL — Port VC Control Register
®
(Intel
Address Offset: 10Ch–10Dh
Default Value:
Bit
15:4 Reserved.
VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However,
3:1 these bits are not applicable since the Intel
0 in the Low Priority Extended VC Count bits in the PVCCAP1 register.
Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not
0
present.
700
High Definition Audio Controller—D27:F0)
00000001h
High Definition Audio Controller—D27:F0)
00000000h
®
High Definition Audio controller reports a 0 in the Low Priority Extended VC
High Definition Audio Controller—D27:F0)
0000h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
®
High Definition Audio controller.
Attribute:
Size:
Description
Attribute:
Size:
Description
®
High Definition Audio controller reports a
RO
32 bits
RO
32 bits
RO
16 bits
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