Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 6

5.13.9 ALT Access Mode .................................................................................. 175
5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode............. 176
5.13.9.2 PIC Reserved Bits.................................................................... 178
5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode............. 178
5.13.10System Power Supplies, Planes, and Signals............................................. 178
5.13.10.1Power Plane Control with SLP_S3#,
5.13.10.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 179
5.13.10.3PWROK Signal ........................................................................ 179
5.13.10.4BATLOW# (Battery Low) (Mobile Only)....................................... 179
5.13.11Clock Generators .................................................................................. 179
5.13.12Legacy Power Management Theory of Operation ....................................... 179
5.13.12.1APM Power Management (Desktop Only) .................................... 180
5.13.12.2Mobile APM Power Management (Mobile Only) ............................. 180
5.13.13Reset Behavior ..................................................................................... 180
5.14 System Management (D31:F0) .......................................................................... 182
5.14.1 Theory of Operation .............................................................................. 182
5.14.1.1 Detecting a System Lockup....................................................... 182
5.14.1.2 Handling an Intruder ............................................................... 183
5.14.1.3 Detecting Improper Flash Programming...................................... 183
5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus.................... 183
5.14.2 TCO Modes .......................................................................................... 183
5.14.2.1 TCO Legacy/Compatible Mode ................................................... 183
5.14.2.2 Advanced TCO Mode ................................................................ 185
5.15 General Purpose I/O (D31:F0) ........................................................................... 186
5.15.1 Power Wells ......................................................................................... 186
5.15.2 SMI# SCI and NMI Routing .................................................................... 186
5.15.3 Triggering............................................................................................ 186
5.15.4 GPIO Registers Lockdown ...................................................................... 186
5.15.5 Serial POST Codes over GPIO ................................................................. 187
5.15.5.1 Theory of Operation................................................................. 187
5.15.5.2 Serial Message Format ............................................................. 188
5.16 SATA Host Controller (D31:F2, F5)..................................................................... 189
5.16.1 SATA 6
5.16.2 SATA Feature Support ........................................................................... 190
5.16.3 Theory of Operation .............................................................................. 191
5.16.3.1 Standard ATA Emulation........................................................... 191
5.16.3.2 48-Bit LBA Operation ............................................................... 191
5.16.4 SATA Swap Bay Support ........................................................................ 191
5.16.5 Hot Plug Operation................................................................................ 191
5.16.5.1 Low Power Device Presence Detection ........................................ 191
5.16.6 Function Level Reset Support (FLR) ......................................................... 192
5.16.6.1 FLR Steps............................................................................... 192
5.16.7 Intel
5.16.7.1 Intel
5.16.8 Power Management Operation ................................................................ 193
5.16.8.1 Power State Mappings.............................................................. 193
5.16.8.2 Power State Transitions............................................................ 194
5.16.8.3 SMI Trapping (APM)................................................................. 195
5.16.9 SATA Device Presence ........................................................................... 195
5.16.10SATA LED ............................................................................................ 196
5.16.11AHCI Operation .................................................................................... 196
5.16.12SGPIO Signals ...................................................................................... 196
5.16.12.1Mechanism ............................................................................. 196
5.16.12.2Message Format...................................................................... 197
5.16.12.3LED Message Type .................................................................. 198
5.16.12.4SGPIO Waveform .................................................................... 199
5.16.13External SATA ...................................................................................... 200
5.17 High Precision Event Timers .............................................................................. 200
5.17.1 Timer Accuracy .................................................................................... 200
5.17.2 Interrupt Mapping................................................................................. 201
5.17.3 Periodic vs. Non-Periodic Modes.............................................................. 201
5.17.4 Enabling the Timers .............................................................................. 202
5.17.5 Interrupt Levels.................................................................................... 202
5.17.6 Handling Interrupts............................................................................... 203
5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 203
5.18 USB EHCI Host Controllers (D29:F0 and D26:F0) ................................................. 204
6
SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#............................... 178
Gb/s Support ............................................................................ 190
®
Rapid Storage Technology Configuration......................................... 192
®
Rapid Storage Manager RAID Option ROM ......................... 193
Datasheet