Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 417

PCI-to-PCI Bridge Registers (D30:F0)
Bit
1
0
11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)
Offset Address: 06h
Default Value:
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
Datasheet
Memory Space Enable (MSE) — R/W. Controls the response as a target for memory
cycles targeting PCI.
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles
targeting PCI.
0 = Disable
1 = Enable
07h
–
0010h
Detected Parity Error (DPE) — R/WC.
0 = Parity error Not detected.
1 = Indicates that the PCH detected a parity error on the internal backbone. This bit gets
set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set.
Description
Attribute: R/WC, RO
Size: 16 bits
Description
417