Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 625

SATA Controller Registers (D31:F5)
15.1.16 SVID—Subsystem Vendor Identification Register
(SATA–D31:F5)
Address Offset: 2Ch
Default Value:
Lockable:
Function Level Reset: No
Bit
Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware
15:0
action taken on this value.
15.1.17 SID—Subsystem Identification Register (SATA–D31:F5)
Address Offset: 2Eh
Default Value:
Lockable:
Bit
Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on
15:0
this value.
15.1.18 CAP—Capabilities Pointer Register (SATA–D31:F5)
Address Offset: 34h
Default Value:
Bit
Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer
7:0 offset is 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is configure as IDE mode
(value of 01).
15.1.19 INT_LN—Interrupt Line Register (SATA–D31:F5)
Address Offset: 3Ch
Default Value:
Function Level Reset: No
Bit
Interrupt Line — R/W. This field is used to communicate to software the interrupt line
7:0
that the interrupt pin is connected to. These bits are not reset by FLR.
15.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F5)
Address Offset: 3Dh
Default Value:
Bit
7:0
Datasheet
2Dh
–
0000h
No
2Fh
–
0000h
No
70h
00h
See Register Description
Interrupt Pin — RO. This reflects the value of D31IP.SIP1 (Chipset Config
Registers:Offset 3100h:bits 11:8).
Attribute: R/WO
Size: 16 bits
Power Well: Core
Description
Attribute: R/WO
Size: 16 bits
Power Well: Core
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
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