Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 448

Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)
Offset
88h–8Bh
8Ch–8Eh
90h–93h
94h–97h
98h–9Bh
A0h–CFh
D0h–D3h
D4h–D5h
D8h–D9h
DCh
E0h–E1h
E2h
E3h
E4h–E7h
E8h–EBh
F0h–F3h
13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)
Offset Address: 00h
Default Value:
Lockable:
Bit
15:0
13.1.2 DID—Device Identification Register (LPC I/F—D31:F0)
Offset Address: 02h
Default Value:
Lockable:
Bit
15:0
448
Mnemonic
GEN2_DEC LPC I/F Generic Decode Range 2
GEN3_DEC LPC I/F Generic Decode Range 3
GEN4_DEC LPC I/F Generic Decode Range 4
USB Legacy Keyboard / Mouse
ULKMC
Control
LGMR LPC Generic Memory Range
Power Management (See
Section
BIOS_SEL1 BIOS Select 1
BIOS_SEL2 BIOS Select 2
BIOS_DEC_EN1 BIOS Decode Enable 1
BIOS_CNTL BIOS Control
FDCAP Feature Detection Capability ID
Feature Detection Capability
FDLEN
Length
FDVER Feature Detection Version
FVECIDX Feature Vector Index
FVECD Feature Vector Data
RCBA Root Complex Base Address
01h
–
8086h
No
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
03h
–
See bit description
No
Device ID — RO. This is a 16-bit value assigned to the PCH LPC bridge. See the
®
Intel 6 Series Chipset Specification Update for the value of the DID Register.
LPC Interface Bridge Registers (D31:F0)
Register Name
13.8.1)
Attribute:
Size:
Power Well:
Description
Attribute:
Size:
Power Well:
Description
Default Type
00000000h R/W
00000000h R/W
00000000h R/W
00000000h R/W
00112233h R/W, RO
4567h R/W
FFCFh R/W, RO
R/WLO, R/W,
00h
RO
0009h RO
0Ch RO
10h RO
00000000h R/W
See
RO
Description
00000000h R/W
RO
16-bit
Core
RO
16-bit
Core
Datasheet