Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 914

23.7 IDE BAR1
Address
Offset
2h
2h
23.7.1 IDDCR—IDE Device Control Register (IDER—D22:F2)
Address Offset: 2h
Default Value:
This register implements the Device Control register of the Control block of the IDE
function. This register is Write only by the Host.
When the HOST reads to the same address it reads the Alternate Status register.
Bit
7:3
2
1
0
23.7.2 IDASR—IDE Alternate status Register (IDER—D22:F2)
Address Offset: 2h
Default Value:
This register implements the Alternate Status register of the Control block of the IDE
function. This register is a mirror register to the status register in the command block.
Reading this register by the HOST does not clear the IDE interrupt of the DEV selected
device
Host read of this register when DEV=0 (Master), Host gets the mirrored data of
IDESD0R register.
Host read of this register when DEV=1 (Slave), host gets the mirrored data of IDESD1R
register.
Bit
7:0
914
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
Register
Symbol
IDDCR IDE Device Control Register
IDASR IDE Alternate status Register
00h
Reserved
Software reset (S_RST) — WO. When this bit is set by the Host, it forces a reset
to the device.
Host interrupt Disable (nIEN) — WO. When set, this bit disables hardware from
sending interrupt to the Host.
Reserved
00h
IDE Alternate Status Register (IDEASR)— RO. This field mirrors the value of the
DEV0/ DEV1 status register, depending on the state of the DEV bit on Host reads.
Register Name
Attribute:
Size:
Description
Attribute:
Size:
Description
Default
Attribute
Value
00h RO, WO
00h RO
WO
8 bits
RO
8 bits
Datasheet