Power Sequencing And Reset Signal Timings - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

Electrical Characteristics
8.7

Power Sequencing and Reset Signal Timings

Table 8-36. Power Sequencing and Reset Signal Timings (Sheet 1 of 2)
Sym
t200
t200a
t200b
t200c
t201
t202
t202a
t203
t204
t205
t206
t207
t208
t210
t211
t212
t213
t214
t215
t217
t218
t219
t220
t221
t222
t223
t224
Datasheet
Parameter
VccRTC active to RTCRST# deassertion
RTCRST# deassertion to DPWROK high
VccDSW3_3 active to DPWROK high
VccDSW3_3 active to VccSus3_3 active
VccSUS active to RSMRST# deassertion
DPWROK high to SLP_SUS#
deassertion
RSMRST# and SLP_SUS# deassertion
to SUSCLK toggling
SLP_S5# high to SLP_S4# high
SLP_S4# high to SLP_S3# high
Vcc active to PWROK high
PWROK deglitch time
VccASW active to APWROK high
PWROK high to PCH clock outputs
stable
PROCPWRGD and SYS_PWROK high to
SUS_STAT# deassertion
SUS_STAT# deassertion to PLTRST#
deassertion
APWROK high to SPI Soft-Start Reads
APWROK high to CL_RST1# deasserted
DMI message and all PCI Express ports
and DMI in L2/L3 state to SUS_STAT#
active
SUS_STAT# active to PLTRST# active
PLTRST# active to PROCPWRGD
inactive
PROCPWRGD inactive to clocks invalid
Clocks invalid to SLP_S3# assertion
SLP_S3# low to SLP_S4# low
SLP_S4# low to SLP_S5# low
SLP_S3# active to PWROK deasserted
PWROK rising to DRAMPWROK rising
DRAMPWROK falling to SLP_S4# falling
Min Max Units
9 — ms
0 — ms
10 — ms
0 — ms
10 — ms
95 — ms
5 — ms
30 µs
30 µs
10 — ms
1 — ms
1 — ms
1 — ms
1 — ms
60 — µs
500 — µs
500 — µs
60 — µs
210 — µs
30 — µs
10 — µs
1 — µs
30 — µs
30 — µs
0 —
0 — µs
-100 — ns
Notes Fig
8-1,
8-2
8-1,
8-2
8-1,
8-2
8-1,
8-2
8-1,
1
8-2
8-1,
2, 3
8-2
8-1,
3, 4
8-2
5 8-3
6 8-3
7, 13
8
9
21
10
8-6
8-6
8-6
8-6
8-6
8-6
8-6
8-6
8-8
11 8-8
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