Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 848

22.1.7 SCC—Sub Class Code
Address Offset: 0Ah
Default Value:
Bit
7:0
22.1.8 BCC—Base Class Code
Address Offset: 0Bh
Default Value:
Bit
7:0
22.1.9 CLS—Cache Line Size
Address Offset: 0Ch
Default Value:
Bit
7:0
22.1.10 LT—Latency Timer
Address Offset: 0Dh
Default Value:
Bit
7:0
22.1.11 HTYPE—Header Type
Address Offset: 0Eh
Default Value:
Bit
7
6:0
848
80h
Sub Class Code (SCC) — RO. Value assigned to the PCH Thermal logic.
11h
Base Class Code (BCC) — RO. Value assigned to the PCH Thermal logic.
00h
Cache Line Size (CLS) — RO. Does not apply to PCI Bus Target-only devices.
00h
Latency Timer (LT) — RO. Does not apply to PCI Bus Target-only devices.
00h
Multi-Function Device (MFD) — RO. This bit is 0 because a multi-function device
only needs to be marked as such in Function 0, and the Thermal registers are not in
Function 0.
Header Type (HTYPE) — RO. Implements Type 0 Configuration header.
Thermal Sensor Registers (D31:F6)
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Datasheet