Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 688

17.1.1.7 SCC—Sub Class Code Register
®
(Intel
Address Offset: 0Ah
Default Value:
Bit
Sub Class Code (SCC) — RO.
7:0
03h = Audio Device
17.1.1.8 BCC—Base Class Code Register
®
(Intel
Address Offset: 0Bh
Default Value:
Bit
Base Class Code (BCC) — RO.
7:0
04h = Multimedia device
17.1.1.9 CLS—Cache Line Size Register
®
(Intel
Address Offset: 0Ch
Default Value:
Bit
Cache Line Size — R/W. Implemented as R/W register, but has no functional impact to
7:0
the PCH
17.1.1.10 LT—Latency Timer Register
®
(Intel
Address Offset: 0Dh
Default Value:
Bit
7:0 Latency Timer — RO. Hardwired to 00
688
High Definition Audio Controller—D27:F0)
03h
High Definition Audio Controller—D27:F0)
04h
High Definition Audio Controller—D27:F0)
00h
High Definition Audio Controller—D27:F0)
00h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
Attribute:
Size:
Description
Attribute:
Size:
Description
Attribute:
Size:
Description
RO
8 bits
RO
8 bits
R/W
8 bits
RO
8 bits
Datasheet