13External Sata; High Precision Event Timers; Timer Accuracy - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

5.16.13 External SATA
The PCH supports external SATA. External SATA utilizes the SATA interface outside of
the system box. The usage model for this feature must comply with the Serial ATA II
Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates
two configurations:
1. The cable-up solution involves an internal SATA cable that connects to the SATA
motherboard connector and spans to a back panel PCI bracket with an eSATA
connector. A separate eSATA cable is required to connect an eSATA device.
2. The back-panel solution involves running a trace to the I/O back panel and
connecting a device using an external SATA connector on the board.
5.17

High Precision Event Timers

This function provides a set of timers that can be used by the operating system. The
timers are defined such that in the future, the operating system may be able to assign
specific timers to used directly by specific applications. Each timer can be configured to
cause a separate interrupt.
The PCH provides eight timers. The timers are implemented as a single counter, each
with its own comparator and value register. This counter increases monotonically. Each
individual timer can generate an interrupt when the value in its value register matches
the value in the main counter.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware can
support an assignable decode space; however, the BIOS sets this space prior to
handing it over to the operating system. It is not expected that the operating system
will move the location of these timers once it is set by the BIOS.
5.17.1

Timer Accuracy

1. The timers are accurate over any 1 ms period to within 0.05% of the time specified
in the timer resolution fields.
2. Within any 100 microsecond period, the timer reports a time that is up to two ticks
too early or too late. Each tick is less than or equal to 100 ns, so this represents an
error of less than 0.2%.
3. The timer is monotonic. It does not return the same value on two consecutive
reads (unless the counter has rolled over and reached the same value).
The main counter is clocked by the 14.31818 MHz clock, synchronized into the
66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized
clock, but does have the correct average period. The accuracy of the main counter is as
accurate as the 14.31818 MHz clock.
200
Functional Description
Datasheet