Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 86

Table 2-26. Power and Ground Signals (Sheet 2 of 2)
Name
VccDFTERM
VccADPLLA
VccADPLLB
VccADAC
Vss
VccAClk
VccAPLLEXP
VccAPLLDMI2
VccAFDIPLL
VccAPLLSATA
VccALVDS
(Mobile Only)
VccTXLVDS
(Mobile Only)
V_PROC_IO
VccDSW3_3
VccSPI
VccSSC
VccClkDMI
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1.8 V or 3.3 V supply for DF_TVS. This pin should be pulled up to 1.8 V or
3.3 V core.
1.05 V supply for Display PLL A Analog Power. This power is supplied by the
core well.
1.05 V supply for Display PLL B Analog Power. This power is supplied by the
core well.
3.3 V supply for Display DAC Analog Power. This power is supplied by the core
well.
Grounds.
1.05 V Analog power supply for internal clock PLL. This power is supplied by
the core well.
NOTE: This pin can be left as no connect
1.05 V Analog Power for DMI. This power is supplied by the core well.
NOTE: This pin can be left as no connect
1.05 V Analog Power for internal PLL. This power is supplied by core well.
NOTE: This pin can be left as no connect
1.05 V analog power supply for the FDI PLL. This power is supplied by core
well.
NOTE: This pin can be left as no connect
1.05 V analog power supply for SATA PLL. This power is supplied by core well.
This rail requires an LC filter when power is supplied from an external VR.
NOTE: This pin can be left as no connect
3.3 V Analog power supply for LVDS, This power is supplied by core well.
1.8 V I/O power supply for LVDS. This power is supplied by core well.
Powered by the same supply as the processor I/O voltage. This supply is used
to drive the processor interface signals. Please refer to the respective
processor documentation to find the appropriate voltage level.
3.3 V supply for Deep S4/S5 wells. If platform does not support Deep S4/S5
then tie to VccSus3_3.
3.3 V supply for SPI Controller Logic. This rail must be powered when VccASW
is powered.
NOTE: This rail can be optionally powered on 3.3 V Suspend power
(VccSus3_3) based on platform needs.
1.05 V supply for Integrated Clock Spread Modulators. This power is supplied
by core well.
1.05 V supply for DMI differential clock buffer
Description
Signal Description
Datasheet