Tco I/O Register Address Map - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

13.9 System Management TCO Registers
The TCO logic is accessed using registers mapped to the PCI configuration space
(Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers,
see LPC Device 31:Function 0 PCI Configuration registers.
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which
is, PMBASE + 60h in the PCI config space. The following table shows the mapping of
the registers within that 32-byte range. Each register is described in the following
sections.
Table 13-12. TCO I/O Register Address Map
TCOBASE
+ Offset
00h–01h
02h
03h
04h–05h
06h–07h
08h–09h
0Ah–0Bh
0Ch–0Dh
0Eh
0Fh
10h
11h
12h–13h
14h–1Fh
13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register
I/O Address:
Default Value:
Lockable:
Bit
15:10 Reserved
TCO Timer Value — R/W. Reading this register will return the current count of the TCO
9:0
timer. Writing any value to this register will reload the timer to prevent the timeout.
534
Mnemonic
TCO Timer Reload and Current
TCO_RLD
Value
TCO_DAT_IN TCO Data In
TCO_DAT_OUT TCO Data Out
TCO1_STS TCO1 Status
TCO2_STS TCO2 Status
TCO1_CNT TCO1 Control
TCO2_CNT TCO2 Control
TCO_MESSAGE1,
TCO Message 1 and 2
TCO_MESSAGE2
TCO_WDCNT Watchdog Control
— Reserved
SW_IRQ_GEN Software IRQ Generation
— Reserved
TCO_TMR TCO Timer Initial Value
— Reserved
TCOBASE +00h
0000h
No
LPC Interface Bridge Registers (D31:F0)
Register Name
Attribute:
Size:
Power Well:
Description
Default Type
0000h R/W
00h R/W
00h R/W
0000h R/WC, RO
0000h R/WC
R/W,
0000h
R/WLO, R/WC
0008h R/W
00h R/W
00h R/W
— —
03h R/W
— —
0004h R/W
— —
R/W
16-bit
Core
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