Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 782

19.1.36 DCAP2—Device Capabilities 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 64h
Default Value:
Bit
31:5 Reserved
Completion Timeout Disable Supported (CTDS) — RO. A value of 1b
4
indicates support for the Completion Timeout Disable mechanism.
Completion Timeout Ranges Supported (CTRS) – RO. This field indicates device
support for the optional Completion Timeout programmability mechanism. This
3:0
mechanism allows system software to modify the Completion Timeout value.
This field is hardwired to support 10 ms to 250 ms and 250 ms to 4 s.
19.1.37 DCTL2—Device Control 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 68h
Default Value:
Bit
15:5 Reserved
Completion Timeout Disable (CTD) — R/W. When set to 1b, this bit disables the
Completion Timeout mechanism.
If there are outstanding requests when the bit is cleared, it is permitted but not
4
required for hardware to apply the completion timeout mechanism to the outstanding
requests. If this is done, it is permitted to base the start time for each request on either
the time this bit was cleared or the time each request was issued.
Completion Timeout Value (CTV) — R/W. This field allows system software to
modify the Completion Timeout value.
0000b = Default range: 40–50 ms (specification range 50 us to 50 ms)
0101b = 40–50 ms (specification range is 16 ms to 55 ms)
0110b = 160–170 ms (specification range is 65 ms to 210 ms)
1001b = 400–500 ms (specification range is 260 ms to 900 ms)
1010b = 1.6–1.7 s (specification range is 1 s to 3.5 s)
3:0
All other values are Reserved.
NOTE: Software is permitted to change the value in this field at any time. For requests
782
67h
–
00000016h
69h
–
0000h
already pending when the Completion Timeout Value is changed, hardware is
permitted to use either the new or the old value for the outstanding requests,
and is permitted to base the start time for each request either on when this
value was changed or on when each request w as issued.
PCI Express* Configuration Registers
Attribute: RO
Size: 32 bits
Description
Attribute: RO, R/W
Size: 16 bits
Description
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