Data Frame Format - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

5.10.5

Data Frame Format

Table 5-20
output from the PCH is AND'd with the PCI input signal. This way, the interrupt can be
signaled using both the PCI interrupt input signal and using the SERIRQ signal (they
are shared).
Table 5-20. Data Frame Format
Data
Frame
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
154
shows the format of the data frames. For the PCI interrupts (A–D), the
Clocks Past
Interrupt Start
Frame
IRQ0 2
IRQ1 5
SMI# 8
IRQ3 11
IRQ4 14
IRQ5 17
IRQ6 20
IRQ7 23
IRQ8 26
IRQ9 29
IRQ10 32
IRQ11 35
IRQ12 38
IRQ13 41
IRQ14 44
IRQ15 47
IOCHCK# 50
PCI INTA# 53
PCI INTB# 56
PCI INTC# 59
PCI INTD# 62
Comment
Ignored. IRQ0 can only be generated using the internal
8524
Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
Ignored. IRQ8# can only be generated internally.
Ignored. IRQ13 can only be generated from FERR#
Not attached to SATA logic
Not attached to SATA logic
Same as ISA IOCHCK# going active.
Drive PIRQA#
Drive PIRQB#
Drive PIRQC#
Drive PIRQD#
Functional Description
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