Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 452

13.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch
Default Value:
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# deassertion.
Bit
Subsystem ID (SSID) — R/WO. This is written by BIOS. No hardware action taken on
31:16
this value.
Subsystem Vendor ID (SSVID) — R/WO. This is written by BIOS. No hardware
15:0
action taken on this value.
13.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h
Default Value:
Lockable:
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These
registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
Bit
31:16
15:7
6:1
0
452
2Fh
–
00000000h
43h
–
00000001h
No
Reserved
Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and
TCO logic. This is placed on a 128-byte boundary.
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
LPC Interface Bridge Registers (D31:F0)
Attribute: R/WO
Size: 32 bits
Description
Attribute: R/W, RO
Size: 32 bit
Usage: ACPI, Legacy
Power Well: Core
Description
Datasheet