Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 758

Table 19-1. PCI Express* Configuration Registers Address Map
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) (Sheet 2 of 3)
Offset
40h–41h
42h–43h
44h–47h
48h–49h
4Ah–4Bh
4Ch–4Fh
50h–51h
52h–53h
54h–57h
58h–59h
5Ah–5Bh
5Ch–5Dh
60h–63h
64h–67h
68h–69h
70h–71h
80h–81h
82h–83h
84h–87h
88h–89h
90h–91h
94h–97h
A0h–A1h
A2h–A3h
A4h–A7h
D4h–D7h
D8h–DBh
DCh–DFh
E1h
E8h–EBh
ECh–EFh
11Ch–143h
104h–107h
758
Mnemonic Register Name
CLIST Capabilities List
XCAP PCI Express* Capabilities
DCAP Device Capabilities
DCTL Device Control
DSTS Device Status
LCAP Link Capabilities
LCTL Link Control
LSTS Link Status
SLCAP Slot Capabilities Register
SLCTL Slot Control
SLSTS Slot Status
RCTL Root Control
RSTS Root Status
DCAP2 Device Capabilities 2 Register
DCTL2 Device Control 2 Register
LCTL2 Link Control 2 Register
MID Message Signaled Interrupt Identifiers
Message Signaled Interrupt Message
MC
Control
Message Signaled Interrupt Message
MA
Address
Message Signaled Interrupt Message
MD
Data
SVCAP Subsystem Vendor Capability
SVID Subsystem Vendor Identification
PMCAP Power Management Capability
PMC PCI Power Management Capability
PCI Power Management Control and
PMCS
Status
MPC2 Miscellaneous Port Configuration 2
MPC Miscellaneous Port Configuration
SMSCS SMI/SCI Status Register
RPDCGEN Rort Port Dynamic Clock Gating Enable
PECR1 PCI Express Configuration Register 1
PECR3 PCI Express Configuration Register 3
— Reserved
UES Uncorrectable Error Status
PCI Express* Configuration Registers
Function 0–5
Default
8010
0041 R/WO, RO
00000FE0h
0000h
0010h R/WC, RO
See bit
description
R/W, WO,
0000h
See bit
description
00000060h R/WO, RO
0000h
0000h R/WC, RO
0000h
00000000h R/WC, RO
00000016h
0000h
0001h
9005h
0000h
00000000h
0000h
A00Dh
00000000h
0001h
C802h
00000000h
00000000h
08110000h
00000000h
00h
00000020h
00000000h
—
See bit
R/WC, RO
description
Datasheet
Type
RO
RO
R/W, RO
R/W, RO,
R/WO
RO
RO
R/W, RO
R/W
RO
R/W, RO
RO
RO
R/W, RO
R/W
R/W
RO
R/WO
RO
RO
R/W, RO
R/W, RO
R/W
R/WC
R/W
R/W
R/W, RO
—