Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 440

12.1.16 CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0)
Address Offset: 34h
Default Value:
Bit
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
7:0
capabilities list is at C8h in configuration space.
12.1.17 INTR—Interrupt Information Register
(Gigabit LAN—D25:F0)
Address Offset: 3Ch–3Dh
Default Value:
Function Level Reset: No
Bit
Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the GbE LAN
controller.
15:8
01h = The GbE LAN controller implements legacy interrupts on INTA.
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
7:0 which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register.
12.1.18 MLMG—Maximum Latency/Minimum Grant Register
(Gigabit LAN—D25:F0)
Address Offset: 3Eh
Default Value:
Bit
7:0 Maximum Latency/Minimum Grant (MLMG) — RO. Not used. Hardwired to 00h.
12.1.19 CLIST 1—Capabilities List Register 1
(Gigabit LAN—D25:F0)
Address Offset: C8h–C9h
Default Value:
Bit
15:8 Next Capability (NEXT) — RO. Value of D0h indicates the location of the next pointer.
Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management
7:0
Register.
440
C8h
0100h
00h
D001h
Gigabit LAN Configuration Registers
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 16 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 16 bits
Description
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