Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 618

Table 15-1. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 2 of 2)
Offset
70h–71h
72h–73h
74h–75h
90h
92h–93h
A8h–ABh
ACh–AFh
B0h–B1h
B2h–B3h
B4h–B5h
C0h
C4h
NOTE: The PCH SATA controller is not arbitrated as a PCI device; therefore, it does not need a
master latency timer.
15.1.1 VID—Vendor Identification Register (SATA—D31:F5)
Offset Address: 00h
Default Value:
Lockable:
Bit
15:0
15.1.2 DID—Device Identification Register (SATA—D31:F5)
Offset Address: 02h
Default Value:
Lockable:
Bit
15:0
618
Mnemonic
PID PCI Power Management Capability ID
PC PCI Power Management Capabilities
PCI Power Management Control and
PMCS
Status
MAP Address Map
PCS Port Control and Status
SATACR0 SATA Capability Register 0
SATACR1 SATA Capability Register 1
FLRCID FLR Capability ID
FLRCLV FLR Capability Length and Value
FLRCTRL FLR Control
ATC APM Trapping Control
ATS ATM Trapping Status
01h
–
8086h
No
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
03h
–
See bit description
No
Device ID — RO. This is a 16-bit value assigned to the PCH SATA controller.
NOTE: The value of this field will change dependent upon the value of the MAP
Register. See Section
SATA Controller Registers (D31:F5)
Register Name
Attribute:
Size:
Power Well:
Description
Attribute:
Size:
Power Well:
Description
and Section 15.1.25
Default Type
See register
RO
description
4003h RO
R/W, RO,
0008h
R/WC
00h R/W
R/W, RO,
0000h
R/WC
0010B012h RO
00000048h RO
0009h RO
2006h RO
0000h R/W, RO
00h R/W
00h R/WC
RO
16 bit
Core
RO
16 bit
Core
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