S3/M3 To S0 Timing Diagram; S5/Moff - S5/M3 Timing Diagram - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

Figure 8-4.

S3/M3 to S0 Timing Diagram

Source
PCH Board
PCH Board
PCH Board
PCH Board
PCH Board
Board
Board
CPU CPU VRM
Board
CPU VRM
Board
Board
PCH
Board PCH
PCH Board
PCH CPU
PCH Board
CPU PCH
PCH CPU/Board
PCH CPU
Figure 8-5.

S5/Moff - S5/M3 Timing Diagram

S o u rc e
P C H
P C H
P C H
P C H
P C H
B o a rd
B o a rd
P C H
P C H
336
Dest Signal Name
SLP_S5#
SLP_S4#
SLP_S3#
SLP_A#
SLP_LAN#
PCH VccASW
PCH Vcc
CPU SVID
CPU VccCore_CPU
PCH SYS_PWROK
t205
PCH PWROK
PCH APWROK
CPU DRAMPWROK
25 MHz
Crystal Osc
PCH
Output Clocks
PROCPWRGD
SUS_STAT#
THRMTRIP#
PLTRST#
DMI
D e s t S ig n a l N a m e
B o a rd S L P _S 5#
B o a rd S L P _S 4#
B o a rd S L P _S 3#
B o a rd S L P _ A #
B o a rd S L P _ L A N #
P C H V ccA S W
P C H A P W R O K
S P I F la sh
C L_ R S T 1 #
C o n tro lle r L in k
(M o b ile O n ly)
PROCPWRGD
Note: V_PROC_IO may go to Vboot at
this time, but can also stay at 0V
(default)
t206
t208
t209
ignored
C o uld a lre a d y be hig h be fo re th is se q ue n ce be g in s (to
sup p o rt W O L), b u t w ill n e ver g o h ig h la ter th a n S L P_A #
t20 7
S P I
t21 3
Electrical Characteristics
Serial VID
Load
V_vid
stable
stable
t210
Assumes soft strap programmed to start at
CPUPWRGD - expected setting for SNB
honored
t211
t2 12
Datasheet