Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 549

LPC Interface Bridge Registers (D31:F0)
13.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register
Offset Address: GPIOBASE +48h
Default Value:
Lockable:
Bit
31:12 Always 0. No corresponding GPIO.
GP_LVL[75:72]— R/W.
These registers are implemented as dual read/write with dedicated storage each. Write
value will be stored in the write register, while read is coming from the read register
which will always reflect the value of the pin. If GPIO[n] is programmed to be an output
(using the corresponding bit in the GP_IO_SEL register), then the corresponding
11:8
GP_LVL[n] write register value will drive a high or low value on the output pin.
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
7:4 Always 0. No corresponding GPIO.
GP_LVL[67:64] — R/W.
These registers are implemented as dual read/write with dedicated storage each. Write
value will be stored in the write register, while read is coming from the read register
which will always reflect the value of the pin. If GPIO[n] is programmed to be an output
(using the corresponding bit in the GP_IO_SEL register), then the corresponding
GP_LVL[n] write register value will drive a high or low value on the output pin.
3:0
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
This register corresponds to GPIO[95:64]. Bit 0 corresponds to GPIO64.
13.10.17 GP_RST_SEL1 — GPIO Reset Select
Offset Address: GPIOBASE +60h
Default Value:
Lockable:
Bit
GP_RST_SEL[31:24] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h
31:24
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
NOTE: GPIO[24] register bits are not cleared by CF9h reset by default.
23:16 Reserved
GP_RST_SEL[15:8] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h
15:8
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
Datasheet
000000C0h
Yes
01000000h
Yes
or 0Eh), or SYS_RESET# assertion.
or 0Eh), or SYS_RESET# assertion.
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
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