Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 871

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.1.8 MEI0_MBAR—MEI0 MMIO Base Address Register
(MEI—D22:F0)
Address Offset: 10h
Default Value:
This register allocates space for the MEI0 memory mapped registers.
Bit
63:4
3
2:1
0
23.1.9 SVID—Subsystem Vendor ID Register
(MEI—D22:F0)
Address Offset: 2Ch
Default Value:
Bit
15:0
23.1.10 SID—Subsystem ID Register
(MEI—D22:F0)
Address Offset: 2Eh
Default Value:
Bit
15:0
Datasheet
17h
–
0000000000000004h
Base Address (BA) — R/W. Software programs this field with the base address of
this region.
Prefetchable Memory (PM) — RO. Indicates that this range is not pre-fetchable.
Type (TP) — RO. Set to 10b to indicate that this range can be mapped anywhere in
64-bit address space.
Resource Type Indicator (RTE) — RO. Indicates a request for register memory
space.
2Dh
–
0000h
Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor
identifier. This field should be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a Word write or as a DWord write with SID register.
2Fh
–
0000h
Subsystem ID (SSID) — R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a Word write or as a DWord write with SVID
register.
Attribute: R/W, RO
Size: 64 bits
Description
Attribute: R/WO
Size: 16 bits
Description
Attribute: R/WO
Size: 16 bits
Description
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