Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 57

Signal Description
Table 2-3. PCI Interface Signals (Sheet 2 of 2)
Name
GNT0# (not
available in
mobile)
GNT1#/ GPIO51
GNT2#/ GPIO53
GNT3#/ GPIO55
CLKIN_PCILOO
PBACK
PCIRST# (not
available in
mobile)
PLOCK# (not
available in
mobile)
SERR# (not
available in
mobile)
PME#
Datasheet
Type
PCI Grants: GNT functionality is Reserved.
GNT[3:1]# pins can instead be used as GPIO.
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
O
NOTES:
1. GNT[3:1]#/GPIO[55,53,51] are sampled as a functional
strap. See
2. GNT[3:0]# functionality is not available.
PCI Clock: This is a 33 MHz clock feedback input to reduce skew
between PCH PCI clock and clock observed by connected PCI
I
devices. This signal must be connected to one of the pins in the
group CLKOUT_PCI[4:0]
O PCI Reset: Reserved.
I/O PCI Lock: Reserved.
I/OD System Error: Reserved.
PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some
cases the PCH may drive PME# active due to an internal wake
event. The PCH will not drive PME# high, but it will be pulled up to
I/OD
VccSus3_3 by an internal pull-up resistor.
Can be used with PCI legacy mode on platforms using a PCIe-to-PCI
bridge. Downstream PCI devices would need to have PME# routed
from the connector to the PCH PME# pin.
Description
Section 2.27 for details.
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