Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 788

19.1.49 MPC—Miscellaneous Port Configuration Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: D8h
Default Value:
Bit
Power Management SCI Enable (PMCE) — R/W.
0 = SCI generation based on a power management event is disabled.
31
1 = Enables the root port to generate SCI whenever a power management event is
Hot Plug SCI Enable (HPCE) — R/W.
30
0 = SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
Link Hold Off (LHO) — R/W.
29
1 = Port will not take any TLP. This is used during loopback mode to fill up the
Address Translator Enable (ATE) — R/W. This bit is used to enable address
translation using the AT bits in this register during loopback mode.
28
0 = Disable
1 = Enable
Lane Reversal (LR) — RO.
This register reads the setting of the PCIELR1 Soft Strap.
0 = PCI Express Lanes 0-3 are reversed.
1 = No Lane reversal (default).
27
NOTE: The port configuration straps must be set such that Port 1 or Port 5 is configured
NOTE: This register is only valid on port 1 (for ports 1–4) or port 5 (for ports 5–8).
Invalid Receive Bus Number Check Enable (IRBNCE) — R/W. When set, the
receive transaction layer will signal an error if the bus number of a Memory request
does not fall within the range between SCBN and SBBN. If this check is enabled and the
request is a memory write, it is treated as an Unsupported Request. If this check is
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enabled and the request is a non-posted memory read request, the request is
considered a Malformed TLP and a fatal error.
Messages, I/O, Config, and Completions are never checked for valid bus number.
Invalid Receive Range Check Enable (IRRCE) — R/W. When set, the receive
transaction layer will treat the TLP as an Unsupported Request error if the address
range of a Memory request does not outside the range between prefetchable and non-
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prefetchable base and limit.
Messages, I/O, Configuration, and Completions are never checked for valid address
ranges.
BME Receive Check Enable (BMERCE) — R/W. When set, the receive transaction
layer will treat the TLP as an Unsupported Request error if a memory read or write
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request is received and the Bus Master Enable bit is not set.
Messages, I/O, Config, and Completions are never checked for BME.
23 Reserved
788
DBh
–
08110000h
detected.
downstream queue.
as a x4 port using lanes 0–3, or 4–7 when Lane Reversal is enabled. x2 lane
reversal is not supported.
PCI Express* Configuration Registers
Attribute: R/W, RO
Size: 32 bits
Description
Datasheet