Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 522

13.8.3.5 GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit
get set, the PCH will generate a Wake Event. Once back in an S0 state (or if already in
an S0 state when the event occurs), the PCH will also generate an SCI if the SCI_EN bit
is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are
reset by a CF9h full reset; bits 63:32 and 15:0 are not. All bits (except bit 35) are reset
by RSMRST#. Bit 35 is reset by DPWROK.
Bit
63:36
35
34:32
31:16
15:14
522
PMBASE + 20h
Attribute:
0000000000000000h
No
Bits 0–34, 56–63:
Bit 35: DSW
Reserved.
GPIO27_STS— R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set at the level specified in GP27IO_POL. Note that
GPIO27 is always monitored as an input for the purpose of setting this bit,
regardless of the actual GPIO configuration.
Reserved.
GPIOn_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set).
If the corresponding enable bit is set in the GPE0_EN register, then when the
GPIO[n]_STS bit is set:
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be
caused depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the
corresponding GPI.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO[15]... and bit 16
corresponds to GPIO[0].
Reserved
LPC Interface Bridge Registers (D31:F0)
Bits 0:32,35 R/WC
Size:
Usage:
Resume,
Description
Bits 33:34, 36:63 RO
64-bit
ACPI
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