Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 663

EHCI Controller Registers (D29:F0, D26:F0)
16.2.1.4 HCCPARAMS—Host Controller Capability Parameters
Register
Offset:
Default Value:
Bit
31:18 Reserved
Asynchronous Schedule Update Capability (ASUC) — R/W. There is no
17
functionality associated with this bit.
Periodic Schedule Update Capability (PSUC) — RO. This field is hardwired to 0b to
16 indicate that the EHC hardware supports the Periodic Schedule Update Event Flag in the
USB2.0_CMD register.
EHCI Extended Capabilities Pointer (EECP) — RO. This field is hardwired to 68h,
15:8 indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI
configuration space.
Isochronous Scheduling Threshold — RO. This field indicates, relative to the
current position of the executing host controller, where software can reliably update the
isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates
the number of micro-frames a host controller hold a set of isochronous data structures
(one or more) before flushing the state. When bit 7 is a 1, then host software assumes
7:4
the host controller may cache an isochronous data structure for an entire frame. Refer
to the EHCI specification for details on how software uses this information for
scheduling isochronous transfers.
This field is hardwired to 8h.
3 Reserved.
Asynchronous Schedule Park Capability — RO. This bit is hardwired to 0 indicating
2
that the host controller does not support this optional feature
Programmable Frame List Flag — RO.
0 = System software must use a frame list length of 1024 elements with this host
1
1 = System software can specify and use a smaller frame list and configure the host
64-bit Addressing Capability — RO. This field documents the addressing range
capability of this implementation. The value of this field determines whether software
should use the 32-bit or 64-bit data structures.
0
This bit is hardwired to 1.
NOTE: The PCH supports 64 bit addressing only.
Datasheet
MEM_BASE + 08h
00006881h
controller. The USB2.0_CMD register (D29:F0, D26:F0:CAPLENGTH + 20h, bits
3:2) Frame List Size field is a read-only register and must be set to 0.
controller using the USB2.0_CMD register Frame List Size field. The frame list must
always be aligned on a 4K page boundary. This requirement ensures that the frame
list is always physically contiguous.
0Bh Attribute:
–
Size:
Description
RO
32 bits
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