Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 810

Table 21-1. Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 2 of 2)
SPIBAR +
Offset
78h–7Bh
7Ch–7Fh
80–83h
84h–87h
88h–8Fh
90h
91h–93h
94h–95h
96h–97h
98h–9Fh
A0h
B0h–B3h
B4h–B7h
B8h–C3h
C0h–C3h
C4–C7h
C8–C11h
D0–D3h
F0–F3h
F4–F7h
F8–FBh
810
Mnemonic
FPR1 Flash Protected Range 1
FPR2 Flash Protected Range 2
FPR3 Flash Protected Range 3
FPR4 Flash Protected Range 4
— Reserved
SSFSTS Software Sequencing Flash Status
SSFCTL Software Sequencing Flash Control
PREOP Prefix Opcode Configuration
OPTYPE Opcode Type Configuration
OPMENU Opcode Menu Configuration
BBAR BIOS Base Address Configuration
FDOC Flash Descriptor Observability Control
FDOD Flash Descriptor Observability Data
— Reserved
AFC Additional Flash Control
LVSCC Host Lower Vendor Specific Component Capabilities
UVSCC Host Upper Vendor Specific Component Capabilities
FPB Flash Partition Boundary
SRDL Soft Reset Data Lock
SRDC Soft Reset Data Control
SRD Soft Reset Data
Serial Peripheral Interface (SPI)
Register Name Default
00000000h
00000000h
00000000h
00000000h
—
00h
0000h
0000h
0000h
00000000
00000000h
00000000h
00000000h
00000000h
—
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Datasheet