Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 585

SATA Controller Registers (D31:F2)
Bit
Device Detection (DET) — RO. Indicates the interface device detection and Phy
state:
3:0
All other values reserved.
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2)
Address Offset:
Default Value:
SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software
controls SATA capabilities. Writes to the SControl register result in an action being
taken by the PCH or the interface. Reads from the register return the last value written
to it.
Bit
31:20 Reserved
19:16 Port Multiplier Port (PMP) — R/W. This field is not used by AHCI.
15:12 Select Power Management (SPM) — R/W. This field is not used by AHCI.
Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which
power states the PCH is allowed to transition to:
11:8
All other values reserved
Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.
This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
7:4
All other values reserved.
The PCH Supports Generation 1 communication rates (1.5 Gb/s), Gen 2 rates
(3.0 Gb/s) and Gen 3 rates (6.0Gb/s)
Datasheet
Value Description
0h No device detected and Phy communication not established
1h Device presence detected but Phy communication not established
3h Device presence detected and Phy communication established
Phy in offline mode as a result of the interface being disabled or
4h
running in a BIST loopback mode
00000000h
Value Description
0h No interface restrictions
1h Transitions to the PARTIAL state disabled
2h Transitions to the SLUMBER state disabled
3h Transitions to both PARTIAL and SLUMBER states disabled
Value Description
0h No speed negotiation restrictions
1h Limit speed negotiation to Generation 1 communication rate
2h Limit speed negotiation to Generation 2 communication rate
3h Limit speed negotiation to Generation 3 communication rate
Description
Attribute: R/W, RO
Size: 32 bits
Description
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