Supported Addresses - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

There are two uses for the PCH's thermal reporting capability:
1. To provide system thermal data to an external controller. The controller can
manage the fans and other cooling elements based on this data. In addition, the
PCH can be programmed by setting appropriate bits in the Alert Enable (AE)
Register (See
device has gone outside of its temperature limits. The alert causes the assertion of
the PCH TEMP_ALERT# (SATA5GP/GPIO49/TEMP_ALERT#) signal. See
Section 5.21.2.6
2. To provide an interface between the external controller and host software. This
software interface has no direct affect on the PCH's thermal collection. It is strictly
a software interface to pass information or data.
The PCH responds to thermal requests only when the system is in S0 or S1. Once the
PCH has been programmed, it will start responding to a request while the system is in
S0 or S1.
To implement this thermal reporting capability, the platform is required to have
appropriate Intel ME firmware, BIOS support, and compatible devices that support the
SMBus protocol.
5.21.2.1

Supported Addresses

The PCH supports 2 addresses: I
reads. These addresses need to be distinct.
The two addresses may be fixed by the external controller, or programmable within the
controller. The addresses used by the PCH are completely programmable.
2
5.21.2.1.1 I C Address
This address is used for writes to the PCH.
• The address is set by soft straps which are values stored in SPI flash and are
defined by the OEM. The address can be set to any value the platform requires.
• This address supports all the writes listed in
• SMBus reads by the external controller to this address are not allowed and result in
indeterminate behavior.
5.21.2.1.2 Block Read Address
This address is used for reads from the PCH.
• The address is set by soft straps or BIOS. It can be set to any value the platform
requires.
• This address only supports SMBus Block Read command and not Byte or Word
Read.
• The Block Read command is supported as defined in the SMBus 2.0 specification,
with the command being 40h, and the byte count being provided by the PCH
following the block read format in the SMBus specification.
• Writes are not allowed to this address, and result in indeterminate behavior.
• Packet Error Code (PEC) may be enabled or not, which is set up by BIOS.
230
Section 22.2 for details on this register) to alert the controller when a
for more details.
2
C Address for writes and Block Read Address for
Functional Description
Table 5-53.
Datasheet