Dma Operation (D31:F0); Channel Priority; Fixed Priority; Pch Dma Controller - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

5.5

DMA Operation (D31:F0)

The PCH supports LPC DMA using the PCH's DMA controller. The DMA controller has
registers that are fixed in the lower 64 KB of I/O space. The DMA controller is
configured using registers in the PCI configuration space. These registers allow
configuration of the channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with
seven independently programmable channels
corresponds to DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to
Channels 5–7. DMA Channel 4 is used to cascade the two controllers and defaults to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to a 1.
Figure 5-3.

PCH DMA Controller

Each DMA channel is hardwired to the compatible settings for DMA device size:
Channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and Channels [7:5]
are hardwired to 16-bit, count-by-words (address shifted) transfers.
The PCH provides 24-bit addressing in compliance with the ISA-Compatible
specification. Each channel includes a 16-bit ISA-Compatible Current Register which
holds the sixteen least-significant bits of the 24-bit address, an ISA-Compatible Page
Register which contains the eight next most significant bits of address.
The DMA controller also features refresh address generation, and auto-initialization
following a DMA termination.
5.5.1

Channel Priority

For priority resolution, the DMA consists of two logical channel groups: Channels 0–3
and Channels 4–7. Each group may be in either fixed or rotate mode, as determined by
the DMA Command Register.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,
a software request for DMA service can be presented through each channel's DMA
Request Register. A software request is subject to the same prioritization as any
hardware request. See the detailed register description for Request Register
programming information in
5.5.1.1

Fixed Priority

The initial fixed priority structure is as follows:
High priority
0, 1, 2, 3
The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the
highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume
the priority position of channel 4 in DMA-2, thus taking priority over Channels 5, 6, and
7.
134
Channel 0
Channel 1
DMA-1
Channel 2
Channel 3
Section 13.2.
Low priority
5, 6, 7
Functional Description
(Figure 5-3). DMA Controller 1 (DMA-1)
Channel 4
Channel 5
DMA-2
Channel 6
Channel 7
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