15.1.21
IDE_TIM — IDE Timing Register (SATA–D31:F5)
Address Offset: Primary:
Default Value:
Bit
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or
Secondary decode.
0 = Disable.
1 = Enables the PCH to decode the associated Command Blocks (1F0–1F7h for primary,
15
This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
NOTE: This bit affects SATA operation in both combined and non-combined ATA modes.
14:0
Reserved
15.1.22
PID—PCI Power Management Capability Identification
Register (SATA–D31:F5)
Address Offset: 70h
Default Value:
Bits
Next Capability (NEXT) — RO. When SCC is 01h, this field will be B0h indicating the
15:8
next item is FLR Capability Pointer in the list.
7:0
Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.
15.1.23
PC—PCI Power Management Capabilities Register
(SATA–D31:F5)
Address Offset: 72h
Default Value:
f
Bits
PME Support (PME_SUP) — RO. By default with SCC = 01h, the default value of
15:11
00000 indicates no PME support in IDE mode.
10
D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported
9
D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported
Auxiliary Current (AUX_CUR) — RO. PME# from D3
8:6
therefore this field is 000b.
Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-
5
specific initialization is required.
4
Reserved
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to
3
generate PME#.
Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI
2:0
Power Management Specification.
626
40h–41h
Secondary: 42h–43h
0000h
170–177h for secondary) and Control Block (3F6h for primary and 376h for
secondary).
See
Section 5.16
for more on ATA modes of operation.
71h
–
B001h
73h
–
4003h
SATA Controller Registers (D31:F5)
Attribute:
R/W
Size:
16 bits
Description
Attribute:
RO
Size:
16 bits
Description
Attribute:
RO
Size:
16 bits
Description
state is not supported,
COLD
Datasheet