Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 851

Thermal Sensor Registers (D31:F6)
22.1.19 TBARB—BIOS Assigned Thermal Base Address
Address Offset: 40h
Default Value:
This BAR creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers. This memory space is active when TBARB.SPTYPEN is
asserted. This BAR is owned by the BIOS, and allows the BIOS to locate the Thermal
registers in system memory space. If both TBAR and TBARB are programmed, then the
OS and BIOS each have their own independent "view" of the Thermal registers, and
must use the TSIU register to denote Thermal registers ownership/availability.
Bit
31:12
11:4
3
2:1
0
22.1.20 TBARBH—BIOS Assigned Thermal Base High DWord
Address Offset: 44h
Default Value:
This BAR extension holds the high 32 bits of the 64 bit TBARB.
Bit
31:0
Datasheet
43h
–
00000004h
Thermal Base Address (TBA) — R/W. This field provides the base address for the
Thermal logic memory mapped configuration registers. 4K B bytes are requested by
hardwiring bits 11:4 to 0s.
Reserved
Prefetchable (PREF) — RO. Indicates that this BAR is NOT pre-fetchable.
Address Range (ADDRNG) — RO. Indicates that this BAR can be located anywhere
in 64 bit address space.
Space Type Enable (SPTYPEN) — R/W.
0 = Disable.
1 = Enable. When set to 1b by software, enables the decode of this memory BAR.
47h
–
00000000h
Thermal Base Address High (TBAH) — R/W. TBAR bits 61:32.
Attribute: R/W,RO
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
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