Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 570

Bits
0
14.1.32 SCLKCG—SATA Clock Gating Control Register
Address Offset: 94h–97h
Default Value:
.
Bit
31:30
29:24
23:9
8:0
570
Port 0 Enabled (P0E) — R/W / RO.
0 = Disabled. The port is in the 'off' state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1). When
MAP.SPD[0] is 1 this is reserved and is read-only 0.
00000000h
Reserved.
Port Clock Disable (PCD) — R/W.
0 = All clocks to the associated port logic will operate normally.
1 = The backbone clock driven to the associated port logic is gated and will not
toggle.
Bit 29: Port 5
Bit 28: Port 4
Bit 27: Port 3
BIt 26: Port 2
Bit 25: Port 1
Bit 24: Port 0
If a port is not available, software shall set the corresponding bit to 1. Software can
also set the corresponding bits to 1 on ports that are disabled.
Software cannot set the PCD [port x]=1 if the corresponding PCS.PxE=1 in either
Dev31Func2 or Dev31Func5 (dual controller IDE mode) or AHCI GHC.PI[x] = "1".
Reserved.
SCLKCG Field 1 — R/W. BIOS must program these bits to 183h.
SATA Controller Registers (D31:F2)
Description
Attribute: R/W
Size: 32 bits
Description
Datasheet